Shakti Microprocessor was invented in the year 2018 by a group of students from IIT Madras .

Shakti is the India's First Microprocessor and it has a good value in the market.This Microprocessor is used in various phones like in phones performance and also some defense purpose , military gadgets .Shakti Microprocessor is build based on family of 6 processor and it is build on RISC-V architecture as follows they are base processors , Multi- core processors and Experimental processors. base processors are divided into three different classes they are E Class , C Class and E Class and similarly Multi-Core processor is also divided into three classes they are M Class , I Class and H Class and finally experimental processor are in development stage it consists of two Classes they are T Class and F Class.

“Shakti Microprocessor”

Students - IIT MADRAS

E Class

• Open source IP supporting RV32/64 - IMAC.
• Optional Direct-mapped caches for instruction and data.
• Supports Machine and User-modes only.
• User-mode trap handling is optional.
• Push button flow to generate variants and subsets of ISA.
• Optimized sequential Multiplier and Divider for ASICs and FPGAs
• OpenOCD based SoC debug support through JTAG.
• OS Ports: FreeRTOS, Zephyr.

C Class

The C Class is a controller class of processors, aimed at mid-range application workloads. The core is a highly optimized, 5-stage in-order design with MMU support and capability to run operating systems Linux and Sel4. These processors are targeted at compute/control applications in the 0.5-1.5 Ghz range. The C-class will supports the full RISC-V ISA. The C Class is also the basis for our Tagged-ISA and Fault tolerant cores.

• Supports RISC-V ISA: RV64IMAFD.
• Compatible with latest privilege spec (v1.10) of RISC-V ISA and supports the sv39/48 virtualization scheme.
• Single and Double Precision Floating point units compliant with IEEE-754.
• Supports the OpenOCD based debug environment through JTAG.
• Includes a High performance branch predictor with a Return-Address-Stack.
• Caches: 16-64KB non-blocking pipelined Instruction and Data caches. Optional L2.
• Includes operand forwarding scheme for better performance.
• Boots RISC-V Linux.

I Class

Equipped with performance oriented features like out-of-order execution, multi-threading, aggressive branch prediction, non-blocking caches and deep pipeline stages. the I-Class processors are targeted at the compute , mobile, storage and networking the mobile and networking segments. Target operating range - 1.5-2.5 Ghz.

M Class

This is a mobile class processor with a maximum of 8 cores, the cores being a combination of C and I class cores. Tile-Link is used as the cache-coherent interconnect used along along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The TileLink topology is customizable to allow optimizations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.

S Class

The S-Class is aimed at Workstation and Enterprise server workloads. The base core is an enhanced version of the I-class, with quad-issue and multi-threading support. A tile-link based cache coherent mesh fabric is the interconnect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherency based on a MOESIF style protocol running on top of Gen-Z.

H Class

SoC configuration aimed at highly parallel enterprise ,HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy is key to achieving a high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory. This aspect of the design is crucial since I/O and memory bandwidth is often the bottleneck for these classes of processors.

T Class

A variant of the C-Class that explores tag based ISAs for object level security. We plan to support coarse and fine grain tags. Coarse grain tags will be used to realize micro-VM like functionality. to mitigate software attacks like buffer-overflow.

F Class

T-Class processors are fault tolerant versions of the base-processors. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics. These are also a key component of our ASIL-D solutions and autonomous vehicle compute blocks.